1. Technical Field
The invention relates generally to semiconductor integrated circuit memory devices and, in particular, to a voltage regulator for controllably adjusting an on-chip generated voltage in response to changes in an external power supply voltage, both voltages comprising inputs to the word line drivers of a memory array. The invention also relates to bandgap reference generators for CMOS devices.
2. Background Art
Dynamic type semiconductor memory devices (DRAMs) are well known. A partial block diagram of a DRAM structure is shown in FIG. 1. The structure comprises a memory array 10 including a plurality of memory cells 12 which function as the memory elements. In this embodiment, each memory cell 12 includes a PFET 14 having its source "S" coupled to a first terminal of a capacitor "C", the second terminal of which is connected to ground. Each row of the plurality of memory cell rows is connected to a word line "WL" through the gate "G" of the respective PFETs 14. Each memory cell is also connected to a bit line "BL" through drain "D" of PFETs 14. The intersections of the word lines are connected to a row decoder (not shown) and the bit lines are connected to a column decoder (not shown). These word lines and bit lines form a matrix definitive of a memory array.
Upon receipt of an externally applied row address signal and column address signal, a particular memory cell is selected which is at the intersection of the word line and the bit line selected by the row decoder and the column decoder, respectively, and the information is read from or written into the memory cell through an input/output interface portion including a sense amplifier 16 connected to the selected bit line and through any input/output buffer. For further specific details on the operation of DRAM structures, U.S. Pat. No. 3,940,747 entitled "High Density, High Speed Random Access Read--Write Memory" can be referred to.
More specific to the invention presented herein, each word line "WL" is connected to a word line driver 18, which selects between one of two voltage levels, such as a first, externally provided power supply voltage V.sub.DD and a second, on-chip generated boost voltage V.sub.BST. For the PMOS transistor memory array configuration depicted, boost voltage V.sub.BST comprises a negative voltage and is used by word line driver 18 to select the corresponding word line as directed by the row decoder (not shown). Power supply voltage V.sub.DD comprises a positive voltage and, with present MOS technology, is typically rated in the range of 2.8-3.3 volts. A negative boost voltage V.sub.BST is desirable to insure the complete discharging of the memory cell capacitors "C" in the selected word line "WL". (Grounding of the selected PFETs would only reduce the cell capacitive voltage to the threshold voltage of the PFETs.) A typical negative boost voltage V.sub.BST is -1 to -2 volts. Because of power requirements, the boost voltage V.sub.BST normally resides across a capacitor 19.
The present invention overcomes the deficiencies of previously known circuitry for providing an on-chip generated boost voltage V.sub.BST. In particular, the present invention provides a regulator which relieves the electric field on the thin oxide of the word line drivers and related circuits without adversely affecting the worst-case memory array response times.